1. Field of the Invention
The invention relates to a manufacturing method for a semiconductor structure, and more particularly, to a manufacturing method for a semiconductor structure applied with strained-silicon technique.
2. Description of the Prior Art
With semiconductor processes entering the era of the deep submicron meter below 65 nanometer (nm), it has been more and more important to increase the metal-oxide semiconductor (MOS) drive current. To improve device performance, strained-silicon technique such as selective epitaxial growth (SEG) method is developed to form epitaxial layers serving as the source/drain of the MOS. Because a lattice constant of the epitaxial layer is different from that of silicon, such characteristic is employed to cause alteration to the band structure of the silicon in the channel region. Accordingly, carrier mobility of the channel region is enhanced and thus device performance is improved.
Please refer to FIG. 1, which is a schematic drawing illustrating a semiconductor structure applied with the conventional SEG method. As shown in FIG. 1, a semiconductor device 150 is positioned on a substrate 100. The semiconductor structure 150 includes a gate 110 and a gate dielectric layer 112. A spacer 114 is formed on the sidewalls of the gate 110 and the gate dielectric layer 112, lightly-doped drains (LDDs) (not shown) are formed in the substrate 100 at two sides of the gate 110, and recesses 120 are respectively formed in the substrate 100 at two sides of the spacer 114. The recess 120 includes an epitaxial layer 112 formed therein. The epitaxial layer 112 is formed by the SEG method and serves as the source/drain by performing ion implantation before or after the SEG method. As shown in FIG. 1, a channel region 130 is formed between the source/drain and underneath the gate 110. The epitaxial layers 122 formed in the source/drain region render compressive or tensile stress to the channel region 130 and thus the carrier mobility in the channel region 130 is enhanced.
However, as size of the semiconductor structure keeps shrinking, the stress provided by the epitaxial layer 122 is more and more susceptible to shapes, configuration, and material choice of the epitaxial layer 122. Furthermore, it is well-known that the epitaxial layer 122 is formed along the surface of the recess 120 during the SEG method. Therefore shapes and crystalline orientation of each surface of the recess 120 also render impacts to the epitaxial layer 122. For example, the recess 120 of the conventional semiconductor device 150 typically includes a V shape, therefore the epitaxial layer 122 formed along the surfaces of the recesses 120 obtains a V-shaped pointed end (as emphasized by circle A). Moreover, it is found that device leakage always occurs at the pointed end.
Therefore, there is still a need for a manufacturing method for a semiconductor structure that is able to form the recesses having the ideal shape, which is beneficial to form the epitaxial layer having a proper shape that improves effective stress to the channel region.